Programmable Devices and Methods of Manufacture Thereof

ABSTRACT

Programmable devices, methods of manufacture thereof, and methods of programming devices are disclosed. In one embodiment, a programmable device includes a link and at least one first contact coupled to a first end of the link. The at least one first contact is adjacent a portion of a top surface of the link and at least one sidewall of the link. The programmable device includes at least one second contact coupled to a second end of the link. The at least one second contact is adjacent a portion of the top surface of the link and at least one sidewall of the link.

The present application is a divisional application of application Ser.No. 12/120,021 filed on May 13, 2008, which is incorporated herein byreference.

TECHNICAL FIELD

The present invention relates generally to the fabrication ofsemiconductor devices, and more particularly to the formation ofprogrammable devices in semiconductor devices and methods of manufacturethereof.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications,such as personal computers, cell phones, digital cameras, and otherelectronic equipment, as examples. Semiconductor devices are typicallyfabricated by sequentially depositing insulating or dielectric layers,conductive layers, and semiconductive layers of material over asemiconductor substrate, and patterning the various material layersusing lithography to form circuit components and elements thereon,forming an integrated circuit.

Fuses are devices that are used in semiconductor devices for manyapplications, such as in array redundancy, electronic chipidentification (EID), recording data such as performance or testparameters, and array repair, as examples. Laser fuses (1-fuses) arefuses that are programmed with a laser. The laser uses a hightemperature to cause a break in a conductive material of the 1-fuses,blowing the 1-fuses. However, 1-fuses require a relatively large amountof surface area on a semiconductor device to avoid causing damage tosurrounding portions of the integrated circuit when the fuses are blown.Furthermore, a special tool is required to program or blow 1-fuses, andthe point in the manufacturing process flow that 1-fuses may beprogrammed is limited to early time periods in the process flow, e.g.,after wafer tests.

Electronic fuses (e-fuses) are fuses that require a smaller amount ofsurface area on a chip than 1-fuses. E-fuses are programmed or blown bythe application of a higher than usual amount of current, which causeselectromigration of a portion of the e-fuse and increases theresistance. E-fuses may be blown at multiple test and application stagesand have a low risk of causing damage to surrounding devices duringprogramming.

Some e-fuse designs have reliability problems because they are requiredto be programmed or blown at large amounts of applied current.

What are needed in the art are improved e-fuses in semiconductor devicesand methods of manufacture thereof.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, andtechnical advantages are generally achieved, by embodiments of thepresent invention, which provide novel programmable devices, fuses,methods of manufacturing semiconductor devices, and methods ofprogramming semiconductor devices.

In accordance with an embodiment of the present invention, aprogrammable device includes a link and at least one first contactcoupled to a first end of the link. The at least one first contact isadjacent a portion of a top surface of the link and at least onesidewall of the link. The programmable device includes at least onesecond contact coupled to a second end of the link. The at least onesecond contact is adjacent a portion of the top surface of the link andat least one sidewall of the link.

The foregoing has outlined rather broadly the features and technicaladvantages of embodiments of the present invention in order that thedetailed description of the invention that follows may be betterunderstood. Additional features and advantages of embodiments of theinvention will be described hereinafter, which form the subject of theclaims of the invention. It should be appreciated by those skilled inthe art that the conception and specific embodiments disclosed may bereadily utilized as a basis for modifying or designing other structuresor processes for carrying out the same purposes of the presentinvention. It should also be realized by those skilled in the art thatsuch equivalent constructions do not depart from the spirit and scope ofthe invention as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIGS. 1 through 3 show cross-sectional views of a semiconductor deviceat various stages of manufacturing in accordance with an embodiment ofthe present invention, wherein a link of a programmable device is formedover a substrate;

FIG. 4 shows a top view of the semiconductor device shown in FIG. 3;

FIG. 5 shows a cross-sectional view of the semiconductor device, whereinthe link and substrate are silicided;

FIG. 6 shows an insulating material disposed over the link and substratein a cross-sectional view;

FIG. 7 illustrates a cross-sectional view of the semiconductor deviceafter the insulating material is patterned with a pattern for at leastone first contact and at least one second contact at ends of the link;

FIG. 8 shows a cross-sectional view of the semiconductor device after aconductive material is deposited over the insulating material, fillingthe patterns;

FIG. 9 shows a cross-sectional view of the semiconductor device after achemical-mechanical polish (CMP) process that removes excess conductivematerial from the top surface of the insulating material, leaving atleast one first contact and at least one second contact formed in theinsulating material;

FIG. 10 shows a top view of the semiconductor device shown in FIG. 9,illustrating the substantially rectangular shape of the at least onefirst contact and the at least one second contact;

FIG. 11 shows a cross-sectional view of the semiconductor device after afirst conductive line and a second conductive line are formed over theat least one first contact and the at least one second contact,respectively;

FIG. 12 shows a top view of the semiconductor device shown in FIG. 11;and

FIG. 13 shows a top view of an embodiment of the present invention,wherein the programmable device comprises one first contact and onesecond contact coupled to ends of a link.

Corresponding numerals and symbols in the different figures generallyrefer to corresponding parts unless otherwise indicated. The figures aredrawn to clearly illustrate the relevant aspects of the preferredembodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention.

The present invention will be described with respect to embodiments in aspecific context, namely, in the formation of fuses in semiconductordevices including static random access memory (SRAM) devices.Embodiments of the present invention may also be applied, however, tosemiconductor devices without SRAM devices and other types ofsemiconductor devices and applications that require the use ofprogrammable devices such as fuses.

In some SRAM devices, three species or types of contacts are used tomake contact from a first metallization layer of the SRAM devices tounderlying material layers and active areas. A first species of contactsmakes contact between the first metallization layer to a substrate orworkpiece. The first species of contacts may make electrical connectionsto sources and drains of transistors, for example. A second species ofcontacts makes contact between the first metallization layer and gatesof the transistors. The second species of contacts are shorter contactsthan the first species of contacts, e.g., having a smaller verticalheight. A third species of contacts of SRAM devices comprise rectangularcontacts or CARECs (an acronym for ContAct, RECtangular), which compriserectangular contacts that provide electrical connections between thefirst metallization layer and underlying regions of the SRAM devices,and also provide electrical connections between portions of the SRAMdevices. The third species of contacts comprising CARECs are rectangularin a top view, and land both on the substrate or workpiece and also ongates of transistors in some applications, for example.

Embodiments of the present invention provide novel electronic fusestructures, methods of fabrication thereof, and methods of programmingsemiconductor devices. In accordance with one embodiment, a fuseincludes a link comprising a silicide formed at a top surface thereof.At least one rectangular contact or CAREC is formed at each end of thelink. A conductive line is coupled to the rectangular contacts at eachend of the link. The fuses may be programmed or blown by applying avoltage across the fuses, causing a current to flow from the rectangularcontact at one end of the link to the other rectangular contact at theother end of the link, e.g., using the conductive lines. The currentcauses a discontinuity to form in the silicide of the link, increasingthe resistance of the link and programming the fuse. The novelrectangular contacts make contact to a top surface of the link,sidewalls of the link, and the substrate. At least a portion of thecurrent may be applied from the substrate or conductive line to the atleast one rectangular contact on the other side of the link during theprogramming process. Rectangular contacts may also be fabricated inother regions of the semiconductor device, e.g., in regions of thesemiconductor device that comprise SRAM devices. Advantageously,introducing a new species of contact in the manufacturing process isavoided, because CARECs, which are common in SRAM devices, are used inthe novel fuses described herein.

An embodiment of the present invention will next be described withreference to FIGS. 1 through 12. FIGS. 1 through 3 show cross-sectionalviews of a semiconductor device 100 at various stages of manufacturingin accordance with an embodiment of the present invention, wherein alink 108 of a programmable device is formed over a substrate 102.Referring first to FIG. 1, a workpiece 102 is provided. The workpiece102 may include a semiconductor substrate, wafer, or body comprisingsilicon or other semiconductor materials, for example. The workpiece 102is also referred to herein as a substrate. The substrate 102 may alsoinclude other active components or circuits, not shown. The substrate102 may comprise single-crystal silicon, for example. The substrate 102may include other conductive layers or other semiconductor elements,e.g., transistors, diodes, etc. Compound semiconductors, GaAs, InP,Si/Ge, or SiC, as examples, may be used in place of silicon. Thesubstrate 102 may comprise a silicon-on-insulator (SOI) substrate orgermanium-on-insulator (GOI) substrate, as examples.

An isolation region 104 is formed in the substrate 102, as shown. Aplurality of isolation regions 104 may be formed across the surface ofthe substrate 102, for example, not shown. The isolation region 104 maybe formed by depositing a layer of photosensitive material and/or hardmask material over the substrate 102 and patterning the layer ofphotosensitive material and/or hard mask using lithography, e.g., byexposure to energy through a lithography mask. The layer ofphotosensitive material is developed, and the layer of photosensitivematerial is used as an etch mask while portions of the optional hardmask are etched away. The layer of photosensitive material and/or hardmask is then used as an etch mask while portions of the substrate 102are etched away. The patterned substrate 102 is then filled in with aninsulating material such as an oxide, nitride, other insulatingmaterials, or multiple layers, liners or combinations thereof, formingthe isolation region 104. The isolation region 104 may comprise apattern in a top view, as shown in FIG. 4, leaving regions of thesubstrate 104 in predetermined patterns. Excess portions of theinsulating material may be removed from over the top surface of thesubstrate using an etch process and/or CMP process, for example.

The isolation regions 104 may comprise field oxide regions, shallowtrench isolation (STI) regions, or thick oxide regions, for example. Theisolation regions 104 may be formed using a LOCal Oxidation of Silicon(LOCOS) method or other methods, for example. The isolation regions 104may be formed during the formation of other isolation regions of thesemiconductor device 100, e.g., during the formation of STI regions forCMOS transistors, SRAM devices, or other memory, analog, or logicdevices in other regions of the semiconductor device 100, not shown.

Next, a layer of material 106 is formed over the substrate 102, e.g.,over a portion of the isolation region 104, as shown in thecross-sectional view of FIG. 2. The layer of material 106 may compriseabout 100 nm or less of a semiconductive material such as polysilicon,amorphous silicon, or other types of semiconductor materials, asexamples. The layer of material 106 may also comprise an insulator, asanother example. Alternatively, the layer of material 106 may compriseother dimensions and materials, for example.

The layer of material 106 may comprise a thickness of about 80 to 100 nmin some embodiments, as an example. The layer of material 106 ispatterned using lithography (e.g., as described for the patterning ofthe substrate 102 to form the isolation region 104), and portions of thelayer of material 106 are removed, forming a link 108 comprised of thelayer of material 106, as shown in FIG. 3 in a cross-sectional view. Atop view of FIG. 3 at 4-4 is shown in FIG. 4. If the layer of material106 comprises polysilicon or other semiconductive material, gates oftransistors (not shown in FIG. 3; see FIG. 11 at 154) may also be formedfrom the layer of material 106 elsewhere on the semiconductor device100, simultaneously with the patterning of the layer of material 106 toform the link 108.

The link 108 comprises a central region 110 and two end regions 112 aand 112 b. The end regions 112 a and 112 b are also referred to hereinas a first end 112 a and a second end 112 b. The link 108 comprises aheight comprising dimension d₁ that comprises substantially thethickness of the layer of material 106 as deposited, e.g., about 100 nmor less. The height or dimension d₁ of the link 108 is also referred toherein, e.g., in the claims, as a first height. The link 108 comprises alength or dimension d₂ of about 500 to 1,000 nm, although alternatively,the length of the link 108 may comprise other dimensions. The length ordimension d₃ of the central region 110 of the link 108, shown in the topview of FIG. 4, may comprise about 200 to 500 nm, althoughalternatively, dimension d₃ may comprise other dimensions.

The first end 112 a and the second end 112 b of the link 108 maycomprise a width or dimension d₄ that may comprise about 500 nm or lessin some embodiments, although alternatively, dimension d₄ may compriseother dimensions. It is favorable in some embodiments for dimension d₄of the first end 112 a and second end 112 b to be as small as possible,yet large enough for one or more CARECs (e.g., first contacts 126 a andsecond contacts 126 b, respectively, shown in FIGS. 9 and 10) to landon, for example. The width or dimension d₄ of the first end 112 a andthe second end 112 b is a function of the size of the CARECs and thenumber of CARECs used in the fuse 140 (not shown in FIG. 4; see thecompleted fuse 140 structure in FIG. 11 including the first contacts 126a and second contacts 126 b that comprise CARECs), for example.

The link 108 comprises a width in the central region 110 comprising adimension d₅, as shown in the top view of FIG. 4. Dimension d₅ maycomprise about 50 nm or less, and in some embodiments, the width ordimension d₅ of the central region 110 of the link 108 may comprise aminimum feature size of the semiconductor device 100. Dimension d₅ mayalso comprise about 50 nm or greater, depending on the technology node,for example. In some embodiments, the width or dimension d₅ may comprisethe minimum feature size or critical dimension (CD) that ismanufacturable for a particular semiconductor device 100 using aparticular lithography system or processes used to manufacture thesemiconductor device 100, for example. Dimension d₅ may comprise aminimum gate width of the technology node of the semiconductor device100, in some applications, as examples.

The first end 112 a and second end 112 b may be wider than the centralregion 110 of the length in some embodiments, as shown, comprising adimension d₄ that is greater than dimension d₃, to accommodate for aplurality of contacts 126 a and 126 b. Alternatively, the first end 112a and the second end 112 b may comprise substantially the same dimensionor may be slightly larger than width or dimension d₅ of the centralregion 110 of the link 108, as shown in FIG. 13 at 212 a and 212 b, tobe described further herein.

The workpiece 102 proximate the top surface and proximate the first end112 a and second end 112 b may comprise a dimension d₆ comprising about100 nm or less. Dimension d₆ of the workpiece 102 may be defined by theisolation regions 104 formed in the workpiece 102. The workpiece 102 mayalso comprise substantially the same width or dimension d₄ of the firstend 112 a and second end 112 b, for example, not shown. Alternatively,the workpiece 102 proximate the first end 112 a and second end 112 b maycomprise other dimensions.

The first end 112 a and second end 112 b may comprise a length ordimension d₇ in a top view of about 500 nm or less, as an example,although alternatively, dimension d₇ may comprise other dimensions. Thearea of the first end 112 a and the second end 112 b may comprise aminimal amount of area, e.g., (dimension d₄× dimension d₇) may be aminimal amount for landing of the contacts 126 a and 126 b on the firstend 112 a and the second end 112 b, respectively. First and second ends112 a and 112 b having a minimal surface area d₄×d₇ is beneficialbecause providing excess silicide (not shown in FIG. 4; see silicide 114in FIG. 5) is avoided, which may interfere with the programming of thefuse 140 and may possibly cause device failures, unintended programmingresults, or reliability problems, for example.

Referring again to FIGS. 3 and 4, the dimensions d₁, d₂, d₃, d₄, d₅ andd₇ of the link 108 and dimension d₆ of the workpiece 102 may varydepending on the desired parameters for the programmable device or fuse140, and may vary as a function of the materials used for the link 108and the current that will be used to program and access the programmabledevice 140 (see FIGS. 11 and 12, which show a portion of the completedsemiconductor device 100). Dimension d₅ may be very small in someapplications for ease of programming the programmable device 140, inorder to require less current to program the programmable device 140,for example.

Sidewalls of the link 108 may be substantially vertical after the etchprocess used to form the link 108, as shown in FIG. 3. This may befavorable in some embodiments to avoid siliciding the sidewalls of thelink 108, for example. The entirety of the link 108 may be formed overthe isolation region 104, as shown.

Next, top portions of the link 108 and top portions of the substrate 102proximate the link 108 are silicided, as shown in the cross-sectionalview of FIG. 5. The silicide 114 may be formed by exposing thesemiconductor device 100 to a gas comprising silane and/or a metal, suchas Ni, Co, Ti, or W, as examples, although alternatively, other metalsmay be used to form the silicide 114. The silicide 114 may comprise athickness of about 50 nm or less, for example, although alternatively,the silicide 114 may comprise other dimensions. The silicide 114 processmay not result in silicide 114 being formed on the sidewalls of the link108, as shown. In some embodiments, the silicide 114 may comprise NiSi,as an example. The silicide 114 may also comprise TiSi, CoSi, WSi, orother types of silicide, for example. The silicide 114 may also beformed using a deposition process, e.g., if the link 108 materialcomprises an insulator.

After the link 108 is silicided, the link includes the material 108 andthe silicide 114; thus, the link 108 will now be referred to herein as alink 108/114. Likewise, after portions of the substrate 102 aresilicided, the substrate includes the substrate 102 and the silicide114; thus, the silicided portions of the substrate 102 will now bereferred to herein as a substrate 102/114.

Next, substantially rectangular contacts 126 a and 126 b are formed overthe ends 112 a and 112 b of the link 108/114, as shown incross-sectional views in FIGS. 6 through 9 and in a top view in FIG. 10.The rectangular contacts 126 a and 126 b are also referred to herein ascontacts, CARECs, or at least one first contact 126 a and at least onesecond contact 126 b, for example. The rectangular contacts 126 a and126 b may be formed in the same manufacturing process steps used to formCARECs of the semiconductor device 100 elsewhere on the workpiece 102,e.g., in SRAM regions. The rectangular contacts 126 a and 126 b may beformed by a subtractive etch process in some embodiments, e.g., byforming a conductive material over the link 108/114 and substrate102/114 and patterning the conductive material to form the rectangularcontacts 126 a and 126 b. However, in other embodiments, the rectangularcontacts 126 a and 126 b are formed using a damascene method. Thepatterns in the lithography mask (not shown) used to pattern therectangular contacts may be rectangular, but when the contacts areactually patterned, the corners may be rounded, resulting insubstantially rectangular-shaped contacts 126 a and 126 b, for example.

In a damascene method, an insulating material 116 is formed over thelink 108/114 and substrate 102/114, the insulating material 116 ispatterned, and the patterned insulating material 116 is filled with aconductive material 120/122 to form the contacts 126 a and 126 b. Forexample, an insulating material 116 is formed over the silicided link108/114 and substrate 102/114, as shown in FIG. 6. The insulatingmaterial 116 may be formed by depositing an oxide or other material,e.g., using a chemical vapor deposition (CVD) or other process. Theinsulating material 116 may comprise an oxide, a nitride, a lowdielectric constant (k) material having a dielectric constant of lessthan 3.9, other insulators, or combinations or multiple layers thereof,for example. In some embodiments, the insulating material 116 comprisessilicon dioxide, for example. The insulating material 116 extends overthe top surface of the link 108 and comprises a greater height than theheight or dimension d₁ (not shown in FIG. 6; see FIG. 3) of the link108/114, as shown. The insulating material 116 may comprise a contact(CA) level inter-level dielectric (ILD) insulating material, forexample. The insulating material 116 comprises a lower portion 116 a andan upper portion 116 b disposed over the lower portion 116 a and thesilicided link 108/114.

The insulating material 116 is patterned using lithography, as describedfor the patterning of the substrate 102 to form the isolation region104, forming patterns 118 for the contacts 126 a and 126 b in theinsulating material 116, as shown in a cross-sectional view in FIG. 7.Patterning the insulating material 116 leaves portions of the topsurface of the silicided link 108/114, portions of the isolation region104, and portions of the silicided substrate 102/114 exposed. Patterningthe insulating material 116 may result in the rounding or sloping of thesidewalls 119 of the silicided link 108/114, due to the etch processused to pattern the insulating material 116, for example, as shown. Ifinsulating sidewall spacers are present on sidewalls of the link108/114, similar to the sidewall spacers 156 on gates 154 of transistors(not shown in FIG. 7; see FIG. 11), the sidewall spacers of the link108/114 are also removed when patterning the insulating material 116,for example. Patterning the insulating material 116 comprises patterningthe upper portion 116 b proximate the top surface of the silicided link108/114, and patterning both the upper portion 116 b and the lowerportion 116 a proximate sidewalls 119 of the link 108/114 and thesilicided workpiece 102/114 proximate the link 108/114.

The patterns 118 in the insulating material 116 are filled with aconductive material 120/122, as shown in a cross-sectional view in FIG.8. For example, an optional liner 120 comprising a conductive materialsuch as Ti, TiN, TaN, other materials, or multiple layers thereof, maybe deposited over the patterned insulating material 116. The liner 120may comprise a thickness of about 30 nm or less, for example. The liner120 may comprise a first layer of Ti and a second layer of TiN disposedover the first layer of Ti, as an example. Alternatively, the liner 120may comprise other materials and dimensions, for example. The liner 120lines the top surfaces and sidewalls of the insulating material 116,portions of the silicide 114 of the link 108/114, portions of thesilicide 114 of the substrate 102/114, and portions of the isolationregion 104 disposed between the substrate 102/114 and the link 108/114.

In some embodiments, forming the optional liner 120 may cause theformation of an optional silicide 124 on sidewalls of the link 108/114,as shown in FIG. 8. For example, if the liner 120 comprises Ti and thematerial 108 of the link 108/114 comprises Si, then a silicide 124comprising TiSi may be formed on the sidewalls of the link 108/114. Thesilicide 124 may comprise a thickness of about 10 nm or less, forexample. Alternatively, the optional silicide 124 may comprise othermaterials and dimensions, for example.

If the liner 120 does not comprise Ti, the silicide 124 may not beformed, for example. As one example, the liner 120 may comprise TaN, andconductive material 122 (to be described further herein) may compriseCu. In such an embodiment, silicide 124 would not be formed, forexample. The silicide 124 may also not be formed if other materials areused for the liner 120 and/or conductive material 122, for example.

A conductive material 122 is then formed over the optional liner 120, asshown in FIG. 8. The conductive material 122 may comprise a materialsuch as W, although alternatively, the conductive material 122 maycomprise other materials, such as Cu, Al, or alloys or combinationsthereof with other metals.

The conductive material 120/122 of the first and second contacts 126 aand 126 b may comprise a material or materials deposited to form othercontacts for other devices of the semiconductor device 100, for example,such as contacts 160 and 162 shown in FIG. 11. In some embodiments, theconductive material 120/122 formed in the insulating material 116comprises a contact (CA) layer of a semiconductor device, e.g., formedafter a front-end of the line (FEOL) process. The CA layer may comprisea first metallization layer of a back-end of the line (BEOL) process insome embodiments, for example.

Excess conductive material 120/122 is then removed from over the topsurface of the insulating material 116 using an etch process and/or aCMP process, as shown in FIG. 9 in a cross-sectional view, leaving firstand second contacts 126 a and 126 b formed in the insulating material116. A top view of the semiconductor device 100 (without the insulatingmaterial 116) in FIG. 9 at 10-10 at this stage of the manufacturingprocess is shown in FIG. 10. The first and second contacts 126 a and 126b may comprise W, Cu, Al, Ti, TiN, TaN, other conductive materials, ormultiple layers or liners thereof in some embodiments, for example.

Two first contacts 126 a are shown in the top view in this embodimentproximate the first end 112 a of the link 108/114, and two secondcontacts 126 b are shown proximate the second end 112 b of the link108/114. Alternatively, only one first contact 126 a and one secondcontact 126 b may be formed. In other embodiments, three or more firstcontacts 126 a and second contacts 126 b may be formed.

The first and second contacts 126 a and 126 b comprise a height ordimension d₉ proximate a first side of the first and second contacts 126a and 126 b. Dimension d₉ may comprise substantially the thickness ofthe upper portion 116 b of the insulating material 116. The first andsecond contacts 126 a and 126 b comprise a height or dimension d₈proximate a second side of the contacts 126 a and 126 b, wherein thesecond side of the contacts 126 a and 126 b is opposite the first sideof the contacts 126 a and 126 b. Dimension d₈ may comprise substantiallythe thickness of the insulating material 116, e.g., the lower portion116 a and the upper portion 116 b of the insulating material 116.Dimension d₈ may be greater than d₉ by an amount substantially equal tothe thickness of the lower portion 116 a of the insulating material 116,for example.

The first side of the first and second contacts 126 a and 126 bcomprises a side that is adjacent, coupled to, and in electrical contactwith the top surface of the link 108/114, e.g., adjacent a portion ofthe silicide 114 of the link 108/114. The second side of the first andsecond contacts 126 a and 126 b comprises a side that is adjacent,coupled to, and in electrical contact with the top surface of thesubstrate 102/114, e.g., adjacent a portion of the substrate 102/114covered with silicide 114. A portion of the first and second contacts126 a and 126 b is coupled to the substrate 102/114, as shown. A portionof the first and second contacts 126 a and 126 b is also coupled to thesidewalls 119 of the link 108/114.

The dimension d₈ is also referred to herein as a third height, anddimension d₉ is also referred to herein as a second height, e.g., in theclaims. In some embodiments, dimension d₈ is greater than the secondheight or dimension d₉ of the contacts 126 a and 126 b, and dimension d₈is also greater than the first height or dimension d₁ of the link108/114, for example. Dimension d₈ may be substantially equal to thetotal or summation of dimensions d₁ and d₉, for example. Some areas orportions of the first and second contacts 126 a and 126 b may have aheight that is greater than the third height or dimension d₈ by aboutthe thickness of about the silicide 114, e.g., in areas of the contacts126 a and 126 b disposed over the isolation regions 104 where thesilicide 114 is not present.

The first and second contacts 126 a and 126 b comprise a substantiallyrectangular shape in the top view of the semiconductor device 100,comprising a length or dimension d₁₀ on a first edge of about 300 nm orless and a width or dimension d₁₁ on a second edge of about 100 nm orless, as examples. Alternatively, dimensions d₁₀ and d₁₁ may compriseother dimensions or values, for example. Dimension d₁₁ may comprise aminimum feature size of the semiconductor device 100, and dimension d₁₀may comprise about 2× to 3× the minimum feature size of thesemiconductor device 100 in some embodiments, for example.

The first and second contacts 126 a and 126 b may comprise CARECscomprising substantially the same shape and size as CARECs formed inother regions of the semiconductor device 100. For example, CARECs maybe formed in SRAM regions of the semiconductor device 100, not shown,wherein the CARECs are used to make electrical contact to portions ofthe SRAM devices and are also used to connect or couple togetherportions of individual SRAM devices. For example, CARECs may be used tomake a connection between two levels of the semiconductor device 100,and also to connect silicide from a top of a polysilicon gate to asilicide on the substrate 102. The CARECs of the SRAM devices (notshown) are also referred to herein as at least one third contact, e.g.,in the claims, to distinguish between the first and second contacts 126a and 126 b.

Advantageously, CARECs that are rectangular and make electrical contactto underlying devices having two different heights, such as dimensionsd₈ and d₉ of the first and second contacts 126 a and 126 b, may alreadybe designed into the semiconductor device 100 manufacturing processflow, and the first and second contacts 126 a and 126 b of theprogrammable devices 140 described herein are advantageously easilyimplemented into the semiconductor device 100 design, in someembodiments. Thus, the introduction of a new species of contact into themanufacturing process flow for the semiconductor device 100 is avoided,which saves engineering time and money for integrating a new species ofcontact and avoids reliability problems, as examples.

The first and second contacts 126 a and 126 b are coupled to a first end112 a and a second end 112 b of the link 108/114, respectively. Forexample, first contacts 126 a are coupled to the first end 112 a (seeFIG. 10), e.g., the left end of the link 108/114 in FIG. 9. Contacts 126a comprise first contacts that are adjacent a portion of a top surfaceof the link 108/114 and are also adjacent at least one sidewall of thelink 108/114 and the substrate 102/114. Second contacts 126 b arecoupled to the second end 112 b, e.g., the right end of the link108/114. Contacts 126 b comprise second contacts that are adjacent aportion of a top surface of the link 108/114 and are also adjacent atleast one sidewall of the link 108/114 and the substrate 102/114.

Next, a first conductive line 130 a is formed over the first contact 126a, and a second conductive line 130 b is formed over the second contact126 b, as shown in FIG. 11. The first conductive line 130 a and thesecond conductive line 130 b may be formed in a conductive line layer ofthe semiconductor device 100. The conductive line layer may comprise ametallization layer M1 of the semiconductor device 100, for example. Theconductive lines 130 a and 130 b may be formed using a damasceneprocess, as described for the contacts 126 a and 126 b, for example.Alternatively, the conductive lines 130 a and 130 b may be formed usinga subtractive etch process, by depositing a conductive material,patterning the conductive material using an etch process, and forming aninsulating material 128 between the patterned conductive lines 130 a and130 b. If the conductive lines 130 a and 130 b comprise Al, for example,a subtractive etch process may be used.

In a damascene process, which may be used if the conductive lines 130 aand 130 b comprise Cu, for example, an insulating material 128 that maycomprise similar materials and dimensions described for insulatingmaterial 116 is formed over the first insulating material 116 and thecontacts 126 a and 126 b. The insulating material 128 is patterned witha pattern for the conductive lines 130 a and 130 b, and a conductivematerial 132/134 is formed over the insulating material 128 to fill thepatterns. The conductive material 132/134 may comprise a liner 132comprising a barrier layer, seed layer, or other conductive linermaterials, and the conductive fill material 134 may comprise Cu, Al, oralloys or combinations thereof, as examples. Alternatively, theconductive material 132/134 may comprise other materials. Excessconductive material 132/134 is then removed from over the top surface ofthe insulating material 128 using an etch and/or CMP process, forexample, leaving the conductive lines 130 a and 130 b formed in theinsulating material 128. Other conductive lines 164 (see region 150) maysimultaneously be formed in other regions of the semiconductor device100 in the same conductive line layer M1 that the conductive lines 130 aand 130 b are formed in, for example.

FIG. 11 also shows another region 150 of the semiconductor device 100elsewhere on the workpiece 102, which may be proximate or spaced apartfrom the fuse 140, in an embodiment of the present invention where theprogrammable device or fuse 140 may be implemented in an SRAMapplication, as an example. Transistors comprising a gate dielectric 152formed over the workpiece 102 and a gate 154 disposed over the gatedielectric are formed in regions 150. The transistors include sidewallspacers 156 formed on sidewalls of the gate 154 and gate dielectric 152.Source and drain regions 158 are formed in the workpiece 102 proximatethe sidewall spacers of the transistor. The gate 154 and source anddrain regions 158 of the transistors may comprise a silicide 114 at atop surface thereof, as shown.

Contacts 160 make electrical connection between conductive lines 164 ininsulating material 128 and the source or drain regions 158 of thetransistor. Contacts 160 comprise a first species of contacts thatextend completely through the insulating material 116, for example.Contacts 162 make electrical connection between conductive lines 164 ininsulating material 128 and the gate 154 of the transistor. Contacts 162comprise a second species of contacts that extend through the upperportion 116 b of the insulating material 116, for example. CARECscomprise a third species of contacts that may also be formed in region150, not shown. The CARECs in region 150 comprise a similar size andshape as first and second contacts 126 a and 126 b of the fuse 140,comprising a portion that extends completely through the insulatingmaterial 116 and another portion that extends only through the upperportion 116 b of the insulating material 116, for example. Thus, thenovel fuse 140 of embodiments of the present invention advantageouslyutilizes an existing species of contacts, in accordance with someembodiments of the present invention, e.g., when implemented in an SRAMdevice or applications, where CARECs are frequently used.

A top view of the semiconductor device 100 including the programmabledevice 140 is shown in FIG. 12. The conductive lines 130 a and 130 breside over and are coupled to the first and second contacts 126 a and126 b, respectively, and make electrical contact to the first and secondcontacts 126 a and 126 b, respectively.

The conductive lines 130 a and 130 b, first and second contacts 126 aand 126 b, and link 108/114 comprise a programmable device or fuse 140.A resistance of the link 108/114 is alterable by applying a voltage,causing a current to flow from the at least one first contact 126 athrough the link 108/114 to the at least one second contact 126 b. Forexample, the silicide 114 of the link 108/114 makes the link 108/114more conductive and decreases the resistance of the link 108/114.Alternatively, if the link 108 comprises an insulator, the silicide 114may provide substantially all of the conductivity for the link 108/114,for example.

If a current i is applied through the structure that has a great enoughmagnitude, electromigration is caused of the silicide 114 of the link108, e.g., proximate the first contact 126 a, causing a discontinuity orbreak 142 in the silicide 114 of the link 108/114, as shown in thecross-sectional view of FIG. 11 and also in the top view of FIG. 12. Thediscontinuity 142 comprises a hole in the silicide 114 that is formed byelectromigration of the silicide 114. The discontinuity 142 may occur onthe link 108/114 proximate or beneath the at least one first contact 126a, for example. The discontinuity or break 142 in the silicide 114 ofthe link 108/114 causes an increase in the resistance of the link108/114, e.g., increasing the resistance of the programmable device 140and programming the device 140. Thus, the resistance of the link 108/114is alterable by electromigration of a material (e.g., the silicide 114)of the link 108/114 when the current is applied.

The larger the break or discontinuity 142 of the link 108/114 afterprogramming, the greater the resistance of the fuse 140 will be,providing an increase in the resistance difference between theprogrammed and unprogrammed states of the fuse 140. In accordance withsome embodiments of the invention, causing the current i to flow altersthe resistance of the link 108/114 significantly, so that the resistancemay subsequently be sensed to determine a programming state of theprogrammable device 140, for example.

The voltage that causes the current i to flow and program the fuse 140may be applied at the conductive lines 130 a and 130 b. The voltage thatcauses the current i or a portion thereof to flow may optionally alsomay be applied at the substrate 102. For example, a first portion of acurrent i₁ may be applied at the first conductive line 130 a and asecond portion of a current i₂ may be applied at the substrate 102, asshown in FIG. 11. Currents i₁ and i₂ pass through the first contact 126a, the link 108/114, and the second contact 126 b. The total current iin the first contact 126 a, the link 108/114, and the second contact 126b comprises a current i that is a summation of the currents i₁ and i₂.The current i then passes to the second conductive line 130 b, as shown.The first portion of the current i₁ may comprise about 80% of thecurrent i and the second portion of the current i₂ may comprise about20% of the current i in some embodiments, for example, althoughalternatively, the current i may be applied in different percentagesthrough the programmable device 140.

To cause the current i to flow and program the device 140, a voltagedifference is applied across the first conductive line 130 a and/or thesubstrate 102 and the second conductive line 130 b. For example, apositive voltage, such as about 1.5 V or greater, may be applied to thefirst conductive line 130 a and/or the substrate 102. A lower voltage,such as about 0 V, may be applied to the second conductive line 130 b.Alternatively, other voltage levels and voltage differences may be usedto cause the current i to flow and program the device 140, for example.

A cap layer 136 comprising an insulating material may be formed over theconductive lines 130 and 130 b and insulating material 128, as shown inFIG. 11. Additional metallization layers may be formed over the barrierlayer 136, e.g., one or more via layers and conductive line layers maybe formed over the semiconductor device 100 and connected to theconductive lines 130 a or 130 b, substrate 102/114, or other devices ofthe integrated circuit to complete the fabrication process, not shown.

In the embodiment shown in FIGS. 1 through 12, the contacts 126 a and126 b comprise two first contacts 126 a and two second contacts 126 b.The first conductive line 130 a is sufficiently large enough to coverand make contact with both of the first contacts 126 a, as shown in thetop view in FIG. 12. Likewise, the second conductive line 130 b issufficiently large enough to cover and make contact with both of thesecond contacts 126 b. Alternatively, three or more first contacts 126 aand three or more second contacts 126 b may be included in theprogrammable device 140, not shown in the figures.

In other embodiments, a programmable device 240 may include only onefirst contact 226 a and one second contact 226 b, as shown in a top viewin FIG. 13. Like numerals are used for the various elements that wereused to describe FIGS. 1 through 12, and to avoid repetition, eachreference number shown in FIG. 13 is not described again in detailherein. Rather, similar materials x02, x04, x06, x08, etc. . . . arepreferably used for the various material layers shown as were used todescribe for FIGS. 1 through 12, where x=1 in FIGS. 1 through 12 and x=2in FIG. 13. The first and second conductive lines 226 a and 226 b may bemade smaller in these embodiments, comprising a width sufficient tocover the single first and second contacts 226 a and 226 b, as shown.The width of the first and second conductive lines 226 a and 226 b maybe slightly greater than the width of the central region 210 of the link208/214 in these embodiments, or the width of the first and secondconductive lines 226 a and 226 b may be substantially the same as thewidth of the central region 210 of the link 208/214, for example.

Only one fuse 140 and 240 is shown in the figures; however, a pluralityof fuses 140 and 240 may be formed simultaneously across the surface ofthe semiconductor device 100 and 200 in some applications, not shown.Tens, hundreds, or thousands of programmable devices 140 and 240 may beformed across a surface of a semiconductor device 100 and 200, forexample.

Embodiments of the present invention include methods of manufacturingsemiconductor devices 100 and 200 and semiconductor devices 100,programmable device 140 and 240, and fuses 140 and 240 manufacturedusing the methods described herein. Embodiments of the present inventionalso include methods of programming semiconductor devices 100 and 200.

For example, in one embodiment, a method of programming a semiconductordevice 100 or 200 includes providing a programmable device 140 or 240,the programmable device 140 or 240 comprising a link 108/114 or 208/214.The programmable device 140 or 240 includes at least one first contact126 a or 226 a coupled to a first end 112 a or 212 a of the link 108/114or 208/214, the at least one first contact 126 a or 226 a being adjacenta portion of a top surface of the link 108/114 or 208/214 and at leastone sidewall of the link 108/114 or 208/214. The programmable device 140or 240 includes at least one second contact 126 b or 226 b coupled to asecond end 112 b or 212 b of the link 108/114 or 208/214, the at leastone second contact 126 b or 226 b being adjacent a portion of the topsurface of the link 108/114 or 208/214 and at least one sidewall of thelink 108/114 or 208/214. The method of programming the semiconductordevice 100 or 200 includes applying a current i from the at least onefirst contact 126 a or 226 a through the link 108/114 or 208/214 to theat least one second contact 126 b or 226 b. Applying the current ialters a resistance of the link 108/114 or 208/214 of the programmabledevice 140 or 240.

Applying the voltage that causes the current i to flow through the link108/114 or 208/214 may comprise applying a voltage of about 1.5 V orgreater, for example, although alternatively, other voltage levels maybe used. Applying the voltage may cause a current i of about 5 mA orgreater to flow, for example, although alternatively, other levels ofcurrent i may also be used. In some embodiments, the programming currenti may comprise about 5 to 10 mA, as an example. The amount of current irequired to program the fuse 140 or 240 may vary as a function of thematerials or dimensions of the link 108/114 or 208/214 and/or number ofcontacts 126 a or 226 a and 126 b or 226 b used, for example.

Before programming, the programmable devices 140 or 240 may comprise aresistance of about 1,000Ω or less, as an example. In the unprogrammedstate with the silicide 114 of the link 108/114 intact, the resistanceof the devices 140 or 240 may be about 100Ω, for example. Afterprogramming, the programmable devices 140 or 240 may comprise aresistance of about 10,000Ω or greater, for example. In someembodiments, after the silicide 114 of the link 108/114 is disturbed,forming the discontinuity 142, the resistance of the programmabledevices 140 or 240 may be about 50,000Ω, or about 10,000 to 100,000Ω,for example. Alternatively, the resistance values of the programmabledevices 140 or 240 may comprise other values, wherein the programmed andunprogrammed states are detectable by a variation in a measuredresistance of the fuses 140 or 240.

The novel fuses 140 and 240 described herein provide flexibility inprogramming and sensing the fuses 140 and 240. For example, the fuses140 and 240 may be programmed or sensed using the workpiece or substrate102 or 202 or the first conductive lines 130 a or 230 a. Advantageously,because the substrate 102 or 202 may be used to sense the programmedstate or resistance, more sensitivity may be provided, because highleakage currents of other devices that may be connected to theconductive lines 130 a or 130 b are avoided.

The programming of the fuses 140 or 240 may be performed beforesingulation, after a wafer test, after a burn-in test, aftersingulation, before packaging, after packaging, or during or after usein an end application, as examples, although alternatively, the novelfuses 140 or 240 may be programmed at different times.

In embodiments wherein a portion of the at least one first contact 126 aor 226 a is coupled to the substrate 102/114, applying the voltage thatcauses the programming current i during the programming process maycomprise applying at least a portion i₂ of the current i to thesubstrate 102/114.

Embodiments of the present invention are beneficial in manyapplications. For examples, the programmable devices 140 and 240 may beused in memory arrays such as SRAM cells, to disable certain areas ofthe memory array. Redundant areas of circuitry, such as memory cells ina memory array may be enabled or disabled by programming the fuses 140and 240, for example. The fuses 140 and 240 may be used to programoptional features of an electronic device, such as a cell phone or MP3player. Another example of an application in which the fuses 140 and 240may be implemented is in EID of the integrated circuit 100 containingthe fuses 140 and 240. Alternatively, embodiments of the presentinvention may be implemented in other applications.

Embodiments of the present invention achieve technical advantages byproviding novel structures for electrically programmable fuses 140 and240 and novel methods of manufacture thereof. The link 108/114 and208/214 may be formed at the same time, e.g., using the same lithographymask and manufacturing processing steps, that gate of transistors ormemory devices are formed, such as gates 154 shown in FIG. 11. Therectangular contacts 126 a, 126 b, 226 a, and 226 b may be formed at thesame time, using the same lithography mask and manufacturing processingsteps, that CARECs of other memory devices such as SRAMs are formed. Therectangular contacts 126 a, 126 b, 226 a, and 226 b may be formed usingthe same lithography step and etch process that contacts 160, 162, andCARECs are formed in region 150 of the semiconductor device 100, forexample. The conductive lines 130 a, 130 b, 230 a, and 230 b may beformed at the same time, using the same lithography mask andmanufacturing processing steps, that other conductive lines 164 inregion 150 of the semiconductor device 100 and 200 are formed. Thus, noadditional lithography masks or processing steps may be required tomanufacture the novel fuses 140 and 240.

Because contacts 126 a, 126 b, 226 a, and 226 b may have a similar shapeand may be formed using a same processing step as existing CARECs inother regions of the semiconductor device 100 and 200 in someembodiments, introducing an additional species or type of contact intothe manufacturing process flow is avoided. Thus, additional maintenanceefforts to ensure reliability of an additional size or type of contactin the manufacturing process flow are advantageously not required.

The rectangular contacts 126 a, 126 b, 226 a, and 226 b are larger thana minimum feature size contact or via, resulting in contacts 126 a, 126b, 226 a, and 226 b that have a high current carrying capability. Theincreased current carrying capability of the contacts 126 a and 226 aenables them to reach a higher temperature during programming. Thus, thediscontinuity or break 142 that forms below the contacts 126 a and 226 afrom the high current used to program the fuses 140 and 240 is larger,which improves the reliability of the fuses 140 and 240 and increasesthe measurable resistance difference between programmed and unprogrammedfuses 140 and 240. Furthermore, the larger rectangular contacts 126 a,126 b, 226 a, and 226 b also have a large cooling access and stay coolduring programming, preventing reliability issues due to overheating.

Because portions of the contacts 126 a, 126 b, 226 a, and 226 b arecoupled to the substrate 102/114, at least a portion i₂ of the current iused to program the fuses 140 and 240 may also be applied through thesubstrate 102/114. Thus, double current routing capability is providedby the novel fuse structures 140 and 240, through the substrate 102/114or conductive lines 130 a or 230 a.

Different routing may be implemented in the semiconductor device 100 or200 for sensing and programming, e.g., by routing to either thesubstrate 102/114 or the conductive lines 130 a, 130 b, 230 a, and 230b, providing flexibility in programming and/or sensing the programmedstate of the fuses 140 and 240. Additional routing opportunities forprogramming and sensing are provided by the novel fuse 140 and 240designs described herein.

The optional routing of current for sensing and programming isadvantageous in applications where large devices such as transistors maybe coupled to the conductive lines 130 a and 130 b, for example. Sometransistors have a large amount of leakage current which comprise anamount of current of a magnitude in the same range as the magnitude ofcurrent used for sensing the fuses 140 or 240 to detect theirprogramming state. In accordance with embodiments of the presentinvention, because the novel first and second contacts 126 a, 126 b, 226a, and 226 b comprise CARECs that contact the substrate 102 and 202 andalso the first conductive lines 130 a and 230 a, the first conductivelines 130 a and 230 a may be used for programming, and the substrate 102and 202 may be used for sensing, for example, so that the sensingoperation is not deleteriously affected by any leakage current that maybe present on the conductive lines 130 a, 130 b, 230 a, or 230 b, forexample.

The optional silicide 124 that may form on the sidewall of the link 108during the formation of the contacts 126 a and 126 b provides anadditional contact or connection of the contacts 126 a and 126 b to thepolysilicon of the link 108. The silicide 124 provides a large interfacearea, which continues to provide electrical connection and contact ofthe contacts 126 a and 126 b to the link 108/114 in the event that thediscontinuity or break region 142 becomes excessively enlarged, in whichcase the silicide 114 may be demigrated below the rectangular contacts126 a during programming, which may end the programming sooner thanintended or cause excessive heating. Thus, the optional silicide 124provides an increased process window, for example.

The positioning of the contacts 126 a, 126 b, 226 a, and 226 b withrespect to the link 108/114 or 208/214 advantageously provides currentdividing and equal distance to the migration area, e.g., proximate thediscontinuity 142 region.

The design of the fuses 140 and 240 advantageously requires a smallamount of area on an integrated circuit. The thin link 108/114 and208/214 that may comprise a width d₅ of a minimum feature size of thesemiconductor device 100 advantageously provides a small silicidereservoir for electromigration. The area (d₄×d₇) shown in FIG. 4 of thefirst end 112 a and second end 112 b of the fuse 140 may be selected anddesigned to be as small as possible, in order to improve reliability.For example, minimizing the area (d₄×d₇) of the first end 112 a andsecond end 112 b of the fuse 140 prevents the presence of an excessiveamount of silicide 114 during the electromigration of the silicide 114during programming of the fuse 140, avoiding the discontinuity region142 being re-filled in with excess silicide 114.

Furthermore, because the first and second contacts 126 a, 126 b, 226 a,and 226 b comprise larger rectangular contacts or CARECs, a large amountof current may be used during programming, for example. The highercurrent that may be used for programming may result in largerdiscontinuity regions 142, for example, leading to a higher measurableresistance of programmed fuses 140, advantageously.

The novel fuses 140 and 240 are easily and inexpensively implementablein manufacturing process flows for semiconductor devices 100. Forexample, the novel fuses 140 and 240 described herein may easily beimplemented into existing manufacturing process flows, lithography maskdesigns, and lithography tools and systems, with few or no additionalprocessing steps being required for implementation of the invention.

Embodiments of the present invention use well-established semiconductordevice manufacturing processes and design species, namely, for CARECs,to form the first and second contacts 126 a, 126 b, 226 a, and 226 b, toproduce fuses 140 and 240 that have a higher current carryingcapability, without requiring the use of an additional contact species.

Embodiments of the invention may be implemented in semiconductorapplications such as transistors, memory devices, logic devices, mixedsignal devices, and other applications, as examples. Embodiments of thepresent invention are particularly advantageous when used insemiconductor devices having SRAM devices in some regions, because aprocess for a CAREC contacts is already be implemented in most SRAMdevice designs. Alternatively, the novel fuses 140 and 240 may also beimplemented in other types of memory devices, such as dynamic randomaccess memory (DRAM) devices, flash memory, or other types of devices,such as logic, analog, mixed signal, or other applications.

Although embodiments of the present invention and their advantages havebeen described in detail, it should be understood that various changes,substitutions and alterations can be made herein without departing fromthe spirit and scope of the invention as defined by the appended claims.For example, it will be readily understood by those skilled in the artthat many of the features, functions, processes, and materials describedherein may be varied while remaining within the scope of the presentinvention. Moreover, the scope of the present application is notintended to be limited to the particular embodiments of the process,machine, manufacture, composition of matter, means, methods and stepsdescribed in the specification. As one of ordinary skill in the art willreadily appreciate from the disclosure of the present invention,processes, machines, manufacture, compositions of matter, means,methods, or steps, presently existing or later to be developed, thatperform substantially the same function or achieve substantially thesame result as the corresponding embodiments described herein may beutilized according to the present invention. Accordingly, the appendedclaims are intended to include within their scope such processes,machines, manufacture, compositions of matter, means, methods, or steps.

What is claimed is:
 1. A method of manufacturing a semiconductor device,the method comprising: forming an isolation region within a substrate;forming a link over the isolation region, the link having a first end, asecond end, and sidewalls; forming a silicide on the link and onportions of the substrate proximate the link; forming at least one firstcontact coupled to the first end and sidewalls of the link and to aportion of the substrate; forming at least one second contact coupled tothe second end and sidewalls of the link and to a portion of thesubstrate; forming a first conductive line over the at least one firstcontact; and forming a second conductive line over the at least onesecond contact.
 2. The method according to claim 1, wherein forming theat least one first contact and the at least one second contactcomprises: forming a first insulating material over the link; patterningthe first insulating material proximate the first end and the second endof the link, exposing the first end and the second end of the link andportions of the substrate proximate the first end and the second end ofthe link; and disposing a conductive material over the patterned firstinsulating material.
 3. The method according to claim 1, wherein thesemiconductor device comprises a minimum feature size, and whereinforming the link comprises forming a link comprising a central regionthat comprises the minimum feature size of the semiconductor device. 4.The method according to claim 3, wherein forming the link, forming theat least one first contact, forming the at least one second contact,forming the first conductive line, and forming the second conductiveline comprise forming a fuse in a first region of the semiconductordevice, wherein forming the at least one first contact and forming theat least one second contact comprise forming contacts comprising asubstantially rectangular shape in a top view of the semiconductordevice, further comprising forming at least one static random accessmemory (SRAM) device in a second region of the semiconductor device,wherein forming the at least one first contact and forming the at leastone second contact further comprises forming at least one third contactof the SRAM device in the second region, the at least one third contactcomprising a substantially rectangular shaped contact (CAREC) in the topview of the semiconductor device.
 5. The method according to claim 1,wherein forming the at least one first contact or forming the at leastone second contact comprises forming a silicide on a sidewall of thelink.
 6. The method according to claim 5, wherein forming the at leastone first contact or forming the at least one second contact comprisesforming Ti, wherein forming the link comprises forming Si, and whereinforming the silicide on the sidewall of the link comprises forming TiSi.7. A method of manufacturing a semiconductor device, the methodcomprising: forming a silicide layer directly on a region of asubstrate; forming an insulating layer over the substrate; forming alink comprising a semiconductor or insulator material and a conductivematerial, wherein the link is formed within the insulating layer,wherein the conductive material is disposed over the semiconductor orinsulator material, wherein the link is disposed on the substrate,wherein the link comprises a first sidewall and an opposite secondsidewall, and wherein the first sidewall and the second sidewallcomprise a silicide sidewall layer covering sidewalls of thesemiconductor or insulator material; forming a first contact in a firstopening in the insulating layer, the first contact coupled to a firstend of the link, the first contact disposed on and physically contactingthe first sidewall of the link, and disposed directly on and physicallycontacting a first portion of the silicide layer, wherein the firstcontact comprises a first conductive liner; forming a second contact ina second opening in the insulating layer, the second contact coupled toa second end of the link, the second contact disposed on the secondsidewall of the link; forming a third contact in a third opening in theinsulating layer, the third contact coupled to the first end of the linkand disposed adjacent the first contact, the third contact disposed onthe first sidewall of the link and disposed directly on and physicallycontacting the first portion of the silicide layer; forming a fourthcontact in a fourth opening in the insulating layer, the fourth contactcoupled to the second end of the link and disposed adjacent the secondcontact, the fourth contact disposed on the second sidewall of the link.8. The method according to claim 7, further comprising: coupling a firstconductive line to the first contact and coupling a second conductiveline to the second contact, the first conductive line formed in ametallization level immediately above the first contact, the firstconductive line physically contacting a top surface of the firstcontact.
 9. The method according to claim 7, wherein the first contactis formed on a first portion of a top surface of the link, and thesecond contact is formed on a second portion of the top surface of thelink.
 10. The method according to claim 7, wherein the first contact andthe second contact comprise substantially rectangular shaped contacts ina top view of the programmable device.
 11. The method according to claim7, wherein the first end of the link and the second end of the link arewider than a central region of the link.
 12. The method according toclaim 7, wherein the semiconductor device comprises a programmabledevice that is located directly on a shallow trench isolation region.13. The method according to claim 7, wherein the first contact and thesecond contact comprise a length on a first edge of about 300 nm or lessand a width on a second edge of about 100 nm or less in a top view ofthe programmable device.
 14. The method according to claim 7, whereinthe first contact and the second contact comprise W, Cu, Al, Ti, TiN, orTaN.
 15. A method of programming a semiconductor device, the methodcomprising: providing a programmable device, the programmable devicecomprising a link, at least one first contact coupled to a first end ofthe link, the at least one first contact being adjacent a portion of atop surface of the link and at least one sidewall of the link, and atleast one second contact coupled to a second end of the link, the atleast one second contact being adjacent a portion of the top surface ofthe link and at least one sidewall of the link; and applying a voltageacross the at least one first contact and the at least one secondcontact, causing a current to flow from the at least one first contactthrough the link to the at least one second contact.
 16. The methodaccording to claim 15, wherein causing the current to flow from the atleast one first contact through the link to the at least one secondcontact alters a resistance of the link of the programmable device. 17.The method according to claim 16, wherein causing the current to flowalters the resistance of the link significantly, so that the resistancemay subsequently be sensed to determine a programming state of theprogrammable device.
 18. The method according to claim 15, whereincausing a current to flow from the at least one first contact throughthe link to the at least one second contact comprises programming theprogrammable device before a singulation process, after a wafer test,after a burn-in test, after a singulation process, before packaging,after packaging, or during or after a use in an end application.
 19. Themethod according to claim 15, wherein providing the programmable devicecomprises providing a programmable device wherein the link is disposedover a substrate, wherein a portion of the at least one first contact iscoupled to the substrate, wherein causing the current to flow from theat least one first contact through the link to the at least one secondcontact comprises applying at least a portion of the voltage at thesubstrate.
 20. The method according to claim 15, wherein providing theprogrammable device comprises providing a programmable device whereinthe link comprises a silicide disposed over a material, wherein causingthe current to flow from the at least one first contact through the linkto the at least one second contact comprises forming a discontinuity inthe silicide of the link.